Description
Item Description:
The primary function of TC358764XBG/TC358765XBG is DSI-to-LVDS Bridge, enabling video streaming output over DSI link to drive LVDS-compatible display panels. The chip supports up to 1366×768 24-bit pixel resolution for single-link LVDS and up to WUXGA (1920×1200 18-bit pixels) resolution for dual-link LVDS. As a secondary function, the chip also supports an I2C Master which is controlled by the DSI link; this may be used as an interface to any other control functions through I2C. The chip can be configured through the DSI link by sending write register commands through DSI Generic Long Write-packets. It can also be configured through the I2C Slave interface.
Product Specs:
| Brand | Toshiba |
| MPN | TC358764XBG |
| Model | TC358764XBG/TC358765XBG |
| Configurable 1- up to 4-Data-Lane DSI Link | bi-directional support on Data Lane 0 |
| Maximum bit rate | 800 Mbps/lane |
| Video input data formats | – RGB565 16 bits per pixel – RGB666 18 bits per pixel – RGB666 loosely packed 24 bits per pixel – RGB888 24 bits per pixel. |
| Video frame size | – Up to 1366×768 24-bit/pixel resolution to single-link LVDS display panel – Up to WUXGA resolutions (1920×1200 18-bit pixels) to dual-link LVDS display panel |
| Maximum pixel clock frequency | 85 MHz |
| Maximum throughput | 297.5 MBytes/sec for single-link or 595 Mbytes/sec for dual-link |
| Supports display | up to 1366×768 24-bit/pixel resolution for single-link, or up to WUXGA (18 bit/pixel) resolutions for dual-link |
| Supports the following pixel formats | RGB666 18 bits per pixel – RGB888 24 bits per pixel |
| Digital Input signals | 3.3V tolerant |
| Digital Output signals | output ranging from 1.8V to 3.3V depending on IO supply voltage |
| MIPI® DSI D-PHY | 1.2 V |
| LVDS PHY | 3.3 V |
| I/O | 1.8 V – 3.3V (all IO supply pins must be same level) |
| Digital Core | 1.2 V |
| Power-down mode | Power Consumption: to 55 µW |
| Normal Operation (2-DSI Data lane @ 200 MHz, Single LVDS @ 27 MHz) | to 157.58 mW |
| Normal Operation (2-DSI Data lane @ 314 MHz, Dual LVDS @ 44.25 MHz each) | to 259.16 mW |
